Kunwar Singh



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  • Profile
  • QualificationsB.Tech, M.Tech, Ph.D (pursuing)
  • DesignationAssistant professor
  • DivisionElectronics and Communications Engineering
  • E-Mailkunwar..research@gmail.com, kunwar.singh@nsit.ac.in, kunwarsingh@dce.ac.in

Biosketch

Mr. Kunwar Singh received his B.Tech in Electronics and Communication Engineering from GGSIP University, New Delhi and M.Tech in VLSI Design from CDAC, Noida in 2006 and 2009 respectively. He served as an intern in Cadence Design Systems during Feb. 2009 – Jul. 2009 where he worked as a product validation engineer in SPB group. He is currently serving as an Assistant Professor in the Division of ECE, NSIT wef Sep. 2013 and is working towards his PhD degree in the University of Delhi. Earlier, he has also served as Assistant Professor in the Department of Electrical Engineering, Delhi Technological University from Jul. 2010 – Sep. 2013. His research interests include Low power high performance digital CMOS circuits, CAD for VLSI Design, applications of artificial intelligence techniques in power-delay-area product optimization of digital CMOS integrated circuits, automated design and optimization of analog and mixed-signal integrated circuits, integrated circuit design using memristors. He has authored and co-authored over 14 research papers in the above areas in various international/national journals and conferences. He has filed one Indian and one US patent application.

Areas of Interest
  1. Low power high performance digital CMOS circuits,
  2. CAD for VLSI Design,
  3. Applications of artificial intelligence techniques in power-delay-area
  4. Product optimization of digital CMOS integrated circuits,
  5. Automated design and optimization of analog and mixed-signal integrated circuits,
  6. Integrated circuit design using memristors.

Patents filed:

1. Title: Method and System for automated design of an integrated circuit using configurable cells. (filed in US)

Published on the official website of World Intellectual Property Organization (WIPO).

Application No. 3282/DEL/2012

Filed on: 25th Oct. 2012

2. Title: Fully static single edge triggered master-slave flip-flop.

Published in the official journal of Indian Patent Office (IPO).

Application No. 211/DEL/2012

Filed on: 24th Jan. 2012

 

International Journals:

1. Kunwar Singh, Satish Chandra Tiwari, and Maneesha Gupta, “A comprehensive comparison between LE and LM based methodologies for optimization of digital circuits”, International Journal of Circuits and Architecture Design (Inderscience Publishers), vol. 1, no. 1, pp. 89-113, 2013.

2. Kunwar Singh, Satish Chandra Tiwari, and Maneesha Gupta,“A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product”,The Scientific World Journal,Volume 2014, Article ID 453675, 14 pages.

3.Satish Chandra Tiwari, Kunwar Singh and Maneesha Gupta, “Automated Transistor width optimization algorithms for Digital circuits”, International Journal of Embedded Systems (Inderscience Publishers), vol. 5, no. 1/2, pp. 44-52, 2013.

4.Satish Chandra Tiwari, Kunwar Singh and Maneesha Gupta, “Design and Development of Logical Effort Based Automated Transistor Width Optimization Methodology”. WASJ (World Applied Science Journal), ISSN 1818-4952, 2012, pages 29-36.

5. Kunwar Singh, Satish Chandra Tiwari, and Maneesha Gupta, “A Master Slave Flip Flop for Low Voltage Systems with Improved Power-Delay Product” WASJ (World Applied Science Journal), ISSN 1818-4952, 2012, pages 45-52.

International Conferences:

1.Satish Chandra Tiwari, Mohammad Ayoub Khan, Kunwar Singh, Ankur Sangal, "Standard Test Bench for Optimization and characterization of Combinational Circuits”, in Proceedings of IEEE International Conference on Signal Processing, Computer and Control pp. 1-5, 2012. (published in IEEExplore Digital Library)

2. Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta, “A High Performance Flip-flop for Low Power Low Voltage Systems” in Proceedings of World Congress on Information and Communication Technologies, pp. 257-262., 2011. (published in IEEExplore Digital Library)

3.Satish Chandra Tiwari, Kunwar Singh, Maneesha Gupta, “Design and Development of Circuit Optimizer using Tcl and SpectreMDL(SPICE) Interface” in Proceedings of World Congress on Information and Communication Technologies, pp. 1385-1389., 2011. (published in IEEExplore Digital Library)

4. Satish Chandra Tiwari, Kunwar Singh, Maneesha Gupta, “Logical Effort based automated Transistor Width Optimization Methodology” in Proceedings of World Congress on Information and Communication Technologies, pp. 1067-1072., 2011. (published in IEEExplore Digital Library)

5.Satish Chandra Tiwari, Kunwar Singh, Maneesha Gupta, “A Novel Methodology for Flip-flop Optimization and Characterization in the NoC Design Space” in Proceedings of World Congress on Information and Communication Technologies, pp. 1067-1072., 2011. (published in IEEExplore Digital Library)

6. Satish Chandra Tiwari, Kunwar Singh, Maneesha Gupta "A Low Power High Density Double Edge Triggered Flip-flop for Low Voltage Systems" in Proceedings of International Conference On Advances in Recent Technologies in Communication and Computing, pp. 377-380., 2010. (published in IEEExplore Digital Library)

7.Manoj Sharma, Arti Noor, Satish Chandra Tiwari, Kunwar Singh, "An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop" in Proceedings of International Conference On Advances in Recent Technologies in Communication and Computing, pp. 478-481., 2009. (published in IEEExplore Digital Library)

National Conferences:

1Kunwar Singh, “A Double Edge Triggered Flip-flop for Low Power Low Voltage Systems” in Proceedings of National Electrical Engineering Conference, New Delhi, December 2011.

2. Arti Noor, Manoj Sharma, Kunwar Singh, Satish Chandra Tiwari, “An Area and Power efficient Double Edge Triggered Flip Flop” in Proceedings of National Conference on VLSI Design ,Embedded Design ,Signals and Systems and Communication Systems” 09 (IEEE sponsored), ISBN-9789380043173.